(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the surface area of a crown shaped capacitor structure.
(2) Description of Prior Art
As performance objectives for semiconductor devices continue to increase efforts to enhance the performance of dynamic random access memory (DRAM), devices, via increases in the surface area of the DRAM capacitor structure, have been ongoing. The greater the surface area of the DRAM capacitor structure, the greater the capacitance, thus allowing the enhanced performance objective to realized. The objective of increasing the surface area for DRAM crown shaped capacitor structures has been successfully addressed by increasing the height of the crown shaped structure. In addition to further increase capacitor surface area the tall, vertical features of the crown shaped capacitor structure are left not embedded, or not located butted to an adjacent insulator region. However continuing to increase only the vertical dimension, or the height of the crown shaped capacitor structure, without increasing the horizontal dimension of this structure, can result in collapse of the tall, unembedded, crown shaped capacitor vertical features, during subsequent fabrication steps. If an insulator layer were retained to butt or embed the DRAM capacitor structure, the outside surfaces of the vertical capacitor features butting the insulator layer would not contribute to the increased surface area objective.
This invention will teach novel process sequences allowing DRAM crown shaped capacitor structures to be formed, featuring the tall vertical capacitor features needed to increase device capacitance To maintain the desired height of the vertical features, as well as to protect against collapse of the tall, vertical capacitor features, a matrix of four individual storage node structures underlying a single top plate structure, is formed to provide the needed surface area. Protection against collapse of the tall vertical storage node features is accomplished via only about 50% of the storage node surface butting an adjacent insulator region. Prior art, such as Ching et al, in U.S. Pat. No. 6,168,989, as well as Huang, in U.S. Pat. No. 6,187,624, describe methods of fabricating crown shaped capacitor structures for DRAM devices, however these prior arts do not describe the novel process sequences described in the present invention, which allow increased capacitor surface area to be realized via the use of a matrix of storage node structures, and with each storage node structure comprised with tall, vertical features, protected only on some sides by adjacent insulator regions.
It is an object of this invention to fabricate crown shaped capacitor structures for DRAM devices.
It is another object of this invention to increase the capacitance of the crown shaped capacitor structure via formation of a matrix of storage node structures, with the complete matrix overlaid with a single top plate structure.
It is still another object of this invention to form storage node structures comprised with tall, vertical features, with a first group of tall vertical feature surfaces butting an adjacent insulator region, while a second group of tall, vertical feature surfaces of the storage node structures remain are stripped of adjacent insulator.
It is still yet another object of this invention to obtain the bare, tall, vertical feature surfaces of the storage node structures via selective removal of insulator regions using a photoresist shape as an etch mask, wherein the photoresist shape is formed in either a positive or in a negative photoresist layer.
In accordance with the present invention a method of increasing the capacitance of a crown shaped capacitor structure via formation of a matrix of storage node structures, wherein each storage node structure is in turn comprised of tall, vertical features, and where a group of the surfaces of the tall vertical features are left uncovered by insulator, is described. After formation of source/drain regions in a semiconductor substrate, capacitor openings are formed in an insulator layer, exposing top portions of the underlying source/drain regions. After formation of a matrix of storage node structures, each located in a specific capacitor opening, a photoresist shape, formed in a positive photoresist layer, is used as a mask to allow regions of the insulator layer to be selectively removed, resulting in a matrix of storage node structures, with each storage node structure comprised with tall vertical features, and with a first portion of tall vertical features still butting the adjacent insulator layer, while a second portion of tall, vertical features have been stripped of insulator layer. After formation of a capacitor dielectric layer on exposed, bare portions of storage node structures, a top plate is formed overlying the matrix of storage node structures, resulting in a capacitor structure with increased surface area as a result of the matrix of storage node structures, each comprised with tall, vertical features, and with a portion of the tall, vertical features stripped of adjacent insulator to further increase surface area maintained bare to further. A second iteration of this invention entails the use of the same photolithographic plate used to define the photoresist shape used to strip adjacent insulator from the sides of the tall, vertical features of the storage node matrix in the first iteration of this invention. However in this case a negative photoresist layer is used to define the photoresist masking shape, thus resulting in insulator stripping of a set tall, vertical features, different then the set of tall, vertical features stripped in the first iteration of this invention.